Track 3: Chiplet Technology & 2.5D/3D Advanced Packaging Chiplet

With the continuous scaling of transistor feature sizes, Moore's Law is gradually reaching its physical limits, and the issues of declining yield and surging costs for large monolithic SoCs using advanced nodes have become increasingly significant. Chiplet technology disaggregates large monolithic SoCs into several functional bare dies and achieves high-speed interconnection at the packaging level, thereby improving yield, reducing costs, and enhancing performance, making it the mainstream architecture for chips in the post-Moore era. 2.5D/3D advanced packaging technologies based on silicon bridges, silicon interposers, TSVs, and hybrid bonding are key to realizing Chiplets. Critical processes in 2.5D/3D packaging, multi-physics simulation and design technologies considering electrical, thermal, and mechanical fields, efficient high-speed interconnect technologies within chiplets, efficient thermal management and heat dissipation technologies, automated KGD (Known Good Die) testing and screening technologies, and the construction of chiplet standardization ecosystems are current research hotspots in related fields. This forum aims to provide a free communication platform for experts, scholars, technicians, and practitioners in this field, sorting out the key trajectories of Chiplet technology and grasping its future development direction through discussions on hot topics in Chiplet technology.

随着晶体管特征尺寸的不断缩小，摩尔定律逐渐达到物理极限，采用先进制程的大面积芯片良率下降和成本上升问题愈发显著。Chiplet技术将大型单片SoC拆分成若干个功能独立的祼芯，在封装层次上实现高速互连，从而达到提升良率、降低成本、增强性能的目标，目前已成为后摩尔时代芯片的主流架构。基于硅桥、硅中介层、TSV、混合键合等2.5D/3D封装技术是实现Chiplet的关键。关于2.5D/3D封装技术中的关键工艺、基于电、热、力多物理场的芯粒仿真和设计技术、芯粒内高效高速互连技术、芯粒的高效热管理和散热技术、芯粒自动化测试筛选KGD技术、芯粒标准化生态构建等是当前相关领域的研究热点。本论坛旨在为本领域内的专家、学者、技术人员、从业者提供一个自由交流平台，通过对Chiplet技术热点问题的讨论，梳理出Chiplet技术的关键脉络，把握技术未来的发展方向。